The present invention relates to programmable circuits. More particularly, the present invention relates to routing of data in a programmable logic device.
Non-volatile memory devices, such as EPROM, EEPROM, and Flash EEPROM, store data even after power is turned off. One common application of EEPROMs is in programmable logic devices (PLDs). PLDs are standard semiconductor components purchased by systems manufacturers in a xe2x80x9cblankxe2x80x9d state that can be custom configured into a virtually unlimited number of specific logic functions. PLDs provide system designers with the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market. PLDs may be reprogrammable, meaning that the logic configuration can be modified after the initial programming.
One type of PLD is known as a Field-Programrnable Gate Array (FPGA). An FPGA is a general purpose device that can be programmed by an end user to perform one or more selected functions. An FPGA typically includes an array of individually programmable logic cells (PLCs), each of which is programmably interconnected to other PLCs and to input/output (I/O) pins via a programmable routing structure to provide the selected function. Examples of such devices are exemplified in U.S. Pat. Nos. 4,642,487; 4,706,216; and 4,758,985.
An FPGA device can be characterized as an integrated circuit that may include four major features:
(1) A user-accessible, configurable memory device, such as SRAM, EPROM, EEPROM, anti-fused, fused, or other, is provided in the FPGA device so as to be at least once-programmable by device users for defining user-provided configuration information. Static Random Access Memory or SRAM is a form of reprogrammable memory that may be differently programmed many times. Electrically Erasable programmable ROM or EEPROM is another example of nonvolatile reprogrammable memory. The configurable memory of an FPGA device may be formed of a mixture of different kinds of memory elements if desired (e.g., SRAM and EEPROM).
(2) Input/Output Blocks (IOBs) are provided for interconnecting other internal circuit components of the FPGA device with external circuitry. The IOBs may have fixed configurations or they may be configurable in accordance with user-provided configuration information.
(3) PLCs are provided for carrying out user-programmed logic functions (e.g., logic gates) as defined by user-provided configuration information. Typically, each of the many PLCs of an FPGA has at least one lookup table (LUT) that is user-configurable to define any desired truth table. A PLC may have other resources such as LUT input signal pre-processing resources and LUT output signal post-processing resources.
(4) An interconnect network is provided for carrying signal traffic within the FPGA device between various PLCs and/or between various IOBs and/or between various IOBs and PLCs. At least part of the interconnect network is typically configurable so as to allow for programmably-defined routing of signals between various PLCs and/or IOBs in accordance with user-defined routing information.
A basic FPGA structure is shown in FIG. 9. This basic structure is repeated over and over within the FPGA. PLCs 2 are used to program logic into the FPGA. The interconnect network is formed by switch boxes 3 and routes 5, which are represented generically by three lines, but may be any number. FIG. 10 is a more detailed illustration of the switch box. For the 8xc3x978 switch box, there are sixty-four switches, shown generally at 6. Each switch is separately controlled as indicated by control signals labeled xe2x80x9cCxe2x80x9d. Unordered bits on one port 7 of the switch are coupled to unordered bits on another port 8 as directed by the control signals. Thus, one characteristic of such current-generation FPGAs is the ability to deliver a very flexible set of logic resources and signal routing resources, such that the end-user can implement nearly any arbitrary logic function.
The evolution of FPGAs from thousands to millions of gates has enabled system-level integration on an FPGA. This level of integration has led to the need to implement a wide variety of very complex functions on FPGAs. Among these more complex functions are a class of functions known as xe2x80x9cdatapathxe2x80x9d functions that are typically characterized by data that is processed in byte-wide or word-wide manner (e.g., 16 bits, 32 bits). Representative functions include 32-bit ADDERS and 16-bitxc3x9716-bit multipliers. For example, U.S. Pat. No. 5,754,459, issued May 19, 1998 to Telikepalli, teaches implementing a multiplier circuit using a number of PLCs in an FPGA architecture. Such functions are typically important in performing Digital Signal Processing (DSP) operations, which are becoming more common in FPGA-based designs.
The data used in DSP operations has the characteristic of being a wide bit-width and a fixed-bit order because the relationship of each bit is maintained for all processing steps. Unfortunately, the architectural flexibility of current FPGAs has become a weakness for implementing DSP functions. For example, the large amount of switches and control signals is inefficient and expensive when implementing wide bit-width and fixed-bit order needed for DSP operations.
Thus, it is desirable to provide a programmable device that can efficiently handle wide bit-width and/or fixed-bit ordered data.
A PLD is disclosed that uses vector routing between components and vector switch boxes to programmably control the vector routing. A vector routing path is coupled between the components and includes a group of wires for routing a group of bits. The bits are routed as one vector so that all bits in the vector are switched at once and as a group by a single set of control signals. Indeed, a single control signal may be used to switch an entire vector routing path. Additionally, the ordering of the bits of the vector is maintained. The vector routing may be between components in a vector domain, within vector-based components, or between components in a PLD domain and a vector domain. The vector routing may be particularly beneficial in DSP operations, where the bit order is maintained through multiple steps.
In another aspect, the vector routing path may allow for time-division multiplexing. For example, different components may use the same vector routing path during different time slices.
In yet another aspect, the vector routing path may be dynamically segmented. Dynamic segmentation allows different portions of the same vector routing path to be used simultaneously by different components. For example, components A and B may communicate with each other via one segment of a vector routing path while two other components C and D communicate on another segment of the same vector routing path. The segmentation may then be dynamically changed.
In yet another aspect, a component may be coupled to multiple vector routing paths through a multiplexer. Consequently, the multiplexer may be dynamically switched such that the component receives information from different component sources.
These and other aspects will become apparent from the following detailed description, which makes references to the accompanying drawings.